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| PM6680 No Rsense dual step-down controller with adjustable voltages for notebook system power Features 6 V to 28 V input voltage range Adjustable output voltages 5V always voltage available deliver 100 mA peak current 1.237 V 1% reference voltage available Lossless current sensing using low side MOSFETs RDS(on) Negative current limit Soft-start internally fixed at 2ms Soft output discharge Latched OVP and UVP Selectable pulse skipping at light loads Selectable minimum frequency (33 kHz) in pulse skip mode 4mW maximum quiescent power Independent power good signals Output voltage ripple compensation VFQFPN-32 5X5 Description PM6680 is a dual step-down controller specifically designed to provide extremely high efficiency conversion, with lossless current sensing technique. The constant on-time architecture assures fast load transient response and the embedded voltage feed-forward provides nearly constant switching frequency operation. An embedded integrator control loop compensates the DC voltage error due to the output ripple. Pulse skipping technique increases efficiency at very light load. Moreover a minimum switching frequency of 33kHz is selectable to avoid audio noise issues. The PM6680 provides a selectable switching frequency, allowing three different values of switching frequencies for the two switching sections. The output voltages OUT1 and OUT2 can be adjusted from 0.9 V to 5.5 V and from 0.9 V to 3.3 V respectively. Applications Notebook computers Tablet PC or slates Mobile system power supply 3-4 cells Li+ battery powered devices Table 1. Device summary Order codes PM6680 PM6680TR Package VFQFPN-32 5mm x 5mm (Exposed pad) VFQFPN-32 5mm x 5mm (Exposed pad) Packaging Tube Tape and reel August 2007 Rev 6 1/49 www.st.com 49 Contents PM6680 Contents 1 2 Simplified application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 2.2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 3.2 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 5 6 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 Constant On time PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Constant on time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . . 22 Pulse skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 No-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Soft start and soft end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Internal linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power up sequencing and operative modes . . . . . . . . . . . . . . . . . . . . . . . 28 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.12.1 7.12.2 7.12.3 7.12.4 Power good signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2/49 PM6680 Contents 7.13 Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.13.1 7.13.2 7.13.3 7.13.4 7.13.5 7.13.6 7.13.7 7.13.8 Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Input capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Closing the integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Other parts design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Design example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3/49 List of figures PM6680 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Simplified application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connection (Through top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5V output efficiency vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.05V output efficiency vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PWM no load input battery vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Skip no load battery current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 No-audible skip no load battery current vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Stand-by mode input battery current vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Shutdown mode input battery current vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5V switching frequency vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.05V switching frequency vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 LDO5 vs output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5V voltage regulation vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.05V voltage regulation vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Voltage reference vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 OUT1, OUT2 and LDO5 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5V load transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.05V load transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5V soft start (0.25 load). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.05V soft start (0.175 load). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5V soft end (No load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.05V soft end (No load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5V soft end (1 Load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.05V soft end (1 Load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5V no-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.05V no-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Constant ON time PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Constant on-time block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Circuitry for output ripple compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PWM and pulse skip mode inductor current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 No audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 RDSON sensing technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Current waveforms in current limit conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Soft start waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Circuitry for output ripple compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Virtual ESR network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 VIN pin filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Inductor current waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Bootstrap circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Current paths, ground connection and driver traces layout . . . . . . . . . . . . . . . . . . . . . . . . 44 Package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4/49 PM6680 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 FSEL pin selection: typical switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 V5SW multifunction pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Operatives modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Protections and operatives modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Inductor manufacturer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Output capacitor manufacturer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Input capacitor manufacturer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 High side MOSFET manufacturer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Low side MOSFET manufacturer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Dual MOSFET manufacturer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Shottky diode manufacturer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 VFQFPN 5x5x1.0 32L Pitch 0.50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Exposed pad variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5/49 1 31 18 19 VCC PGND 22 HGATE1 PHASE1 LGATE1 CSENSE1 V5SW OUT1 COMP1 SGND2 PGOOD1 PGOOD2 SHDN FB1 FB2 NC 6 28 FB1 7 COMP2 2 OUT2 8 PGND 14 1 SGND PGND CSENSE2 12 PGND LGATE2 13 PHASE2 11 HGATE2 21 15 20 PGND SGND 29 SGND 30 16 26 27 5 PGOOD1 EN2 EN1 VREF SKIP FSEL PGOOD2 17 10 23 BOOT1 BOOT2 LDO5 VIN 4 25 32 24 3 6/49 Figure 1. V+ BOOT1 + VIN SGND PGND SGND V+ BOOT2 Simplified application schematic VIN SGND 9 1 1 OUT1+ + + O 1 1 O Simplified application schematic OUT1- PM6680 Simplified application schematic SGND V+ V+ SGND FB1 SGND SGND SGND SGND PM6680 PM6680 Electrical data 2 2.1 Electrical data Maximum rating Table 2. Absolute maximum ratings Parameter V5SW, LDO5 to PGND VIN to PGND HGATEx and BOOTx, to PHASEx PHASEx to PGND CSENSEx , to PGND CSENSEx to BOOTx LGATEx to PGND FBx, COMPx, SKIP, , FSEL,VREF to SGND1,SGND2 PGND to SGND1,SGND2 SHDN,PGOODx, OUTx, VCC, ENx to SGND1,SGND2 Power dissipation at TA = 25C Maximum withstanding voltage range test condition: CDF-AEC-Q100-002- "Human Body Model" acceptance criteria: "Normal Performance" 1. PHASE to PGND up to -2.5 V for t<10 ns 2. LGATEx to PGND up to -1 V for t<40 ns Value -0.3 to 6 -0.3 to 36 -0.3 to 6 -0.6 (1) Unit V V V V V V V V V V W V to36 -0.6 to 42 -6 to 0.3 -0.3 (2) to LDO5 +0.3 -0.3 to Vcc +0.3 -0.3 to 0.3 -0.3 to 6 2.8 VIN Other pins 1000 2000 2.2 Thermal data Table 3. Symbol RthJA TSTG TJ Thermal data Parameter Thermal resistance junction to ambient Storage temperature range Junction operating temperature range Value 35 -40 to 150 -10 to 125 Unit C/W C C 7/49 Pin settings PM6680 3 3.1 Pin settings Connections Figure 2. Pin connection (Through top view) PM6680 8/49 PM6680 Pin settings 3.2 Functions Table 4. N Pin functions Pin Function Signal ground. Reference for internal logic circuitry. It must be connected to the signal ground plan of the power supply. The signal ground plan and the power ground plan must be connected together in one point near the PGND pin. DC voltage error compensation pin for the switching section 2 Frequency selection pin. It provides a selectable switching frequency, allowing three different values of switching frequencies for the switching sections. Enable input for the switching section 2. * The section 2 is enabled applying a voltage greater than 2.4V to this pin. * The section 2 is disabled applying a voltage lower than 0.8V. When the section is disabled the High Side gate driver goes low and Low Side gate driver goes high. If both EN1 and EN2 pins are low and SHDN pin is high the device enters in standby mode. Shutdown control input. * The device switch off if the SHDN voltage is lower than the device off threshold (Shutdown mode) * The device switch on if the SHDN voltage is greater than the device on threshold. The SHDN pin can be connected to the battery through a voltage divider to program an undervoltage lockout. In shutdown mode, the gate drivers of the two switching sections are in high impedance (high-Z). Not connected. Feedback input for the switching section 2 This pin is connected to a resistive voltage-divider from OUT2 to PGND to adjust the output voltage from 0.9V to 3.3V. Output voltage sense for the switching section 2.This pin must be directly connected to the output voltage of the switching section. Bootstrap capacitor connection for the switching section 2. It supplies the high-side gate driver. High-side gate driver output for section 2. This is the floating gate driver output. Switch node connection and return path for the high side driver for the section 2.It is also used as negative current sense input. Positive current sense input for the switching section 2. This pin must be connected through a resistor to the drain of the synchronous rectifier (RDSON sensing) to obtain a positive current limit threshold for the power supply controller. Low-side gate driver output for the section 2. Power ground. This pin must be connected to the power ground plan of the power supply. Low-side gate driver output for the section 1. 1 SGND1 2 3 COMP2 FSEL 4 EN2 5 SHDN 6 7 NC FB2 8 9 10 11 OUT2 BOOT2 HGATE2 PHASE2 12 CSENSE2 13 14 15 LGATE2 PGND LGATE1 9/49 Pin settings Table 4. N 16 PM6680 Pin functions (continued) Pin SGND2 Function Signal ground for analog circuitry. It must be connected to the signal ground plan of the power supply. Internal 5V regulator bypass connection. * If V5SW is connected to OUT5 (or to an external 5V supply) and V5SW is greater than 4.9V, the LDO5 regulator shuts down and the LDO5 pin is directly connected to OUT5 through a 3 (max) switch. If V5SW is connected to GND, the LDO5 linear regulator is always on. 5V internal regulator output. It can provide up to 100mA peak current. LDO5 pin supplies embedded low side gate drivers and an external load. Device supply voltage input and battery voltage sense. A bypass filter (4 and 4.7F) between the battery and this pin is recommended. Positive current sense input for the switching section 1. This pin must be connected through a resistor to the drain of the synchronous rectifier (RDSON sensing) to obtain a positive current limit threshold for the power supply controller. Switch node connection and return path for the high side driver for the section 1.It is also used as negative current sense input. High-side gate driver output for section 1. This is the floating gate driver output. Bootstrap capacitor connection for the switching section 1. It supplies the high-side gate driver. Pulse skipping mode control input. * If the pin is connected to LDO5 the PWM mode is enabled. * If the pin is connected to GND, the pulse skip mode is enabled. * If the pin is connected to VREF the pulse skip mode is enabled but the switching frequency is kept higher than 33KHz (No-audible pulse skip mode). Enable input for the switching section 1. * The section 1 is enabled applying a voltage greater than 2.4V to this pin. * The section 1 is disabled applying a voltage lower than 0.8V. When the section is disabled the High Side gate driver goes low and Low Side gate driver goes high. Power Good output signal for the section 1. This pin is an open drain output and when the output of the switching section 1 is out of +/- 10% of its nominal value.It is pulled down. Power Good output signal for the section 2. This pin is an open drain output and when the output of the switching section 2 is out of +/- 10% of its nominal value.It is pulled down. Feedback input for the switching section 1. This pin is connected to a resistive voltage-divider from OUT1 to PGND to adjust the output voltage from 0.9V to 5.5V. 17 V5SW 18 19 LDO5 VIN 20 CSENSE1 21 22 23 PHASE1 HGATE1 BOOT1 24 SKIP 25 EN1 26 PGOOD1 27 PGOOD2 28 FB1 10/49 PM6680 Table 4. N 29 30 31 32 Pin settings Pin functions (continued) Pin OUT1 COMP1 VCC VREF Function Output voltage sense for the switching section 1.This pin must be directly connected to the output voltage of the switching section. DC voltage error compensation pin for the switching section 1. Device Supply Voltage pin. It supplies all the internal analog circuitry except the gate drivers (see LDO5). Connect this pin to LDO5. Internal 1.237V high accuracy voltage reference. It can deliver 50uA. Bypass to SGND with a 100nF capacitor to reduce noise. 11/49 Electrical characteristics PM6680 4 Electrical characteristics VIN = 12V, TA = 0C to 85C, unless otherwise specified Table 5. Symbol Electrical characteristics Parameter Test condition Min Typ Max Unit Supply section VIN Vcc Input voltage range IC supply voltage Turn-on voltage threshold VV5SW Turn-off voltage threshold Hysteresis VV5SW Rdson Maximum operating range LDO5 internal bootstrap switch resistance OUTx,OUTx discharge-mode on-resistance OUTx,OUTx discharge-mode synchronous rectifier Turn-on level Pin Ish Isb Operating power consumption Operating current sunk by VIN Operating current sunk by VIN FBx > VREF, Vref in regulation, V5WS to 5V SHDN connected to GND, ENx to GND, V5SW to GND 14 190 0.2 V5SW > 4.9 1.8 18 4.6 20 Vout = Vref, LDO5 in regulation 5.5 4.5 4.8 4.75 50 5.5 3 25 28 5.5 4.9 V V V V mV V 0.36 0.6 V 4 18 250 mW A A Shutdown section Device On threshold VSHDN Device Off threshold 1.2 0.8 1.5 0.85 1.7 0.9 V V Soft start section Soft start ramp time Current limit and zero crossing comparator ICSENSE Input bias current limit Comparator offset Zero crossing comparator offset Fixed negative current limit threshold VCSENSE-VPGND VPGND - VPHASE VPGND - VPHASE 90 -6 -1 -120 100 110 6 11 A mV mV mV 2 3.5 ms 12/49 PM6680 Table 5. Symbol On time pulse width FSEL to GND Ton On time duration FSEL to VREF FSEL to LDO5 OFF time TOFFMIN Minimum off time OUT1=1.5V OUT2=1.05V OUT1=1.5V OUT2=1.05V OUT1=1.5V OUT2=1.05V Electrical characteristics Electrical characteristics (continued) Parameter Test condition Min Typ Max Unit 550 230 375 175 285 125 650 270 445 210 340 150 750 315 515 ns 245 395 175 350 500 ns Voltage reference Voltage accuracy VREF Load regulation Undervoltage lockout fault threshold Integrator FB FB Voltage accuracy Input bias current Normal mode Over voltage clamp COMP Under voltage clamp Line regulation Both SMPS, 6V 13/49 Electrical characteristics Table 5. Symbol PM6680 Electrical characteristics (continued) Parameter Test condition Min Typ Max Unit High and low gate drivers HGATEx high state(pullup) HGATE driver on-resistance HGATEx low state (pulldown) LGATEx high state(pullup) LGATE driver on-resistance LGATEx low state (pulldown) 2.0 1.6 1.4 0.8 3 2.7 2.1 1.2 PGOOD pins UVP/OVP protections OVP UVP Over voltage threshold Under voltage threshold Upper threshold (VFB-VREF) PGOOD1,2 Lower threshold (VFB-VREF) IPGOOD1,2 PGOOD leakage current VPGOOD1,2 forced to 5.5V ISink = 4mA 150 88 91 94 1 250 % uA mV Both SMPS sections with respect to VREF. 112 65 107 116 68 110 120 71 113 % % % VPGOOD1,2 Output low voltage Thermal shutdown TSDN Shutdown temperature 150 C Power management pins SMPS disabled level EN1,2 SMPS enabled level Low level (2) FSEL Frequency selection range Middle level High level Pulse skip mode SKIP PWM mode Ultrasonic mode (2) (2) (2) (2) 0.8 V 2.4 0.5 1.0 VLDO5-0.8 0.5 1.0 VLDO5-0.8 1 1 1 1 A VLDO5-1.5 V VLDO5-1.5 V (2) VEN1,2= 0 to 5V Input leakage current VSKIP= 0 to 5V VSHDN= 0 to 5V VFSEL= 0 to 5V 1. by design 2. by demoboard test 14/49 PM6680 Typical operating characteristics 5 Typical operating characteristics FSEL = GND (200/300KHz), SKIP = GND (skip mode), V5SW = V5SW=EXT5V (external 5V power supply connected), input voltage VIN = 12V, SHDN, EN1 and EN2 high, OUT1 = 1.5V, OUT2 = 1.05V, no load unless specified) Figure 3. 1.5V output efficiency vs load current Figure 4. 1.05V output efficiency vs load current Figure 5. PWM no load input battery vs Figure 6. input voltage Skip no load battery current 15/49 Typical operating characteristics Figure 7. No-audible skip no load battery current vs input voltage Figure 8. PM6680 Stand-by mode input battery current vs input voltage Figure 9. Shutdown mode input battery Figure 10. 1.5V switching frequency vs current vs input voltage load current Figure 11. 1.05V switching frequency vs Figure 12. LDO5 vs output current load current 16/49 PM6680 Figure 13. 1.5V voltage regulation vs load current Typical operating characteristics Figure 14. 1.05V voltage regulation vs load current Figure 15. Voltage reference vs load current Figure 16. OUT1, OUT2 and LDO5 power-up Figure 17. 1.5V load transient Figure 18. 1.05V load transient 17/49 Typical operating characteristics Figure 19. 1.5V soft start (0.25 load) PM6680 Figure 20. 1.05V soft start (0.175 load) Figure 21. 1.5V soft end (No load) Figure 22. 1.05V soft end (No load) Figure 23. 1.5V soft end (1 Load) Figure 24. 1.05V soft end (1 Load) 18/49 PM6680 Figure 25. 1.5V no-audible skip mode Typical operating characteristics Figure 26. 1.05V no-audible skip mode 19/49 Block diagram PM6680 6 Block diagram Figure 27. Functional block diagram VIN VCC REFERENCE GENERATOR VREF 5V LINEAR REGULATOR 4V + - UVLO VREF LDO5 ENABLE NC 4.8V LDO5 + UVLO FB2 V5SW OUT2 SKIP FSEL FREQUENCY SELECTOR OUT1 BOOT2 BOOT1 FB1 VCC HGATE2 LEVEL SHIFTER OUT2 SMPS CONTROLLER OUT1 SMPS CONTROLLER LEVEL SHIFTER HGATE1 PHASE2 CSENSE2 COMP2 LDO5 LGATE2 PGOOD2 PHASE1 CSENSE1 COMP1 LDO5 LGATE1 PGOOD1 SHDN STARTUP CONTROLLER TERMIC FAULT LDO5 ENABLE EN1 EN2 UVLO TERMIC CONTROLLER 20/49 PM6680 Device description 7 Device description The PM6680 is a dual step-down controller dedicated to provide logic voltages for notebook computers. It is based on a Constant On Time control architecture. This type of control offers a very fast load transient response with a minimum external component count. A typical application circuit is shown in Figure 27. The PM6680 regulates two adjustable output voltages: OUT1 and OUT2. The switching frequency of the two sections can be adjusted to 200/300kHz, 300/400kHz or 400/500kHz respectively. In order to maximize the efficiency at light load condition, a pulse skipping mode can be selected. The PM6680 includes also a 5V linear regulator (LDO5) that can power the switching drivers. If the output OUT1 regulates 5V, in order to maximize the efficiency in higher consumption status, the linear regulator can be turned off and their outputs can be supplied directly from the switching outputs. The PM6680 provides protection versus overvoltage, undervoltage and over temperature as well as power good signals for monitoring purposes. An external 1.237V reference is available. 7.1 Constant On time PWM control If the SKIP pin is tied to 5V, the device works in PWM mode. Each power section has an independent on time control.The PM6680 employees a pseudo-fixed switching frequency, Constant On Time (COT) controller as core of the switched mode section. Each power section has an independent COT control. The COT controller is based on a relatively simple algorithm and uses the ripple voltage due to the output capacitor's ESR to trigger the fixed on-time one-shot generator. In this way, the output capacitor's ESR acts as a current sense resistor providing the appropriate ramp signal to the PWM comparator. On-time one-shot duration is directly proportional to the output voltage, sensed at the OUT1/OUT2 pins, and inversely proportional to the input voltage, sensed at the VIN pin, as follows: Equation 1 V OUT T ON = K -------------V IN This leads to a nearly constant switching frequency, regardless of input and output voltages. When the output voltage goes lower than the regulated voltage Vreg, the on-time one shot generator directly drives the high side MOSFET for a fixed on time allowing the inductor current to increase; after the on time, an off time phase, in which the low side MOSFET is turned on, follows. Figure 28 shows the inductor current and the output voltage waveforms in PWM mode. 21/49 Device description Figure 28. Constant ON time PWM control PM6680 The duty cycle of the buck converter in steady state is: Equation 2 V OUT D = -------------V IN The PWM control works at a nearly fixed frequency fSW: Equation 3 V OUT -------------V IN f SW = ------------------------------ = 1 K on V OUT K on x -------------V IN As mentioned the steady state switching frequency is theoretically independent from battery voltage and from output voltage. Actually the frequency depends on parasitic voltage drops that are present during the charging path(high side switch resistance, inductor resistance(DCR)) and discharging path(low side switch resistance, DCR). As a result the switching frequency increases as a function of the load current. Standard switching frequency values can be selected for both sections by pin FSEL as shown in the following table: Table 6. FSEL pin selection: typical switching frequency Fsw@OUT1=1.5V(kHz) FSEL = GND FSEL = VREF FSEL = LDO5 200 290 390 Fsw@OUT2=1.05V(kHz) 325 425 590 22/49 PM6680 Device description 7.2 Constant on time architecture Figure 29 shows the simplified block diagram of a Constant On Time controller. A minimum off-time constrain (300ns typ.) is introduced to allow inductor valley current sensing on synchronous switch. A minimum on-time (70ns) is also introduced to assure the start-up switching sequence. PM6680 has a one-shot generator for each power section that turns on the high side MOSFET when the following conditions are satisfied simultaneously: the PWM comparator is high, the synchronous rectifier current is below the current limit threshold, and the minimum off-time has timed out. Once the on-time has timed out, the high side switch is turned off, while the synchronous switch is turned on according to the anti-cross conduction circuitry management. When the negative input voltage at the PWM comparator (Figure 29), which is a scaleddown replica of the output voltage (see the external R1/R2 divider in Figure 29), reaches the valley limit (determined by internal reference Vr = 0.9V), the low-side MOSFET is turned off according to the anti-cross conduction logic once again, and a new cycle begins. Figure 29. Constant on-time block diagram Toff-min Toff- BOOT CSENSE Positive Current Limit Vr + + - PWM S R Ton Q Q Level shifte r HS driver HGATE PHASE COMP gm + + 0.5V 0.25V + Comparato r LDO5 LS driver Vr FB OUT Zero-cross. Zero- S R Q LGATE PGND + - Comp. VIN SKIP LDO5 0.5V bandga p 1.236V Vr + - VREF 23/49 Device description PM6680 7.3 Output ripple compensation and loop stability In a classic Constant On Time control, the system regulates the valley value of the output voltage and not the average value, as shown in Figure 28 In this condition, the output voltage ripple is source of a DC static error. To compensate this error, an integrator network can be introduced in the control loop, by connecting the output voltage to the COMP1/COMP2 (for the OUT1 and OUT2 sections respectively) pin through a capacitor CINT as in Figure 30 Figure 30. Circuitry for output ripple compensation COMP PIN VOLTAGE Vr t OUTPUT VOLTAGE V V Vr COMP CFILT CINT I=gm(V1-Vr) PWM Comparator gm + - VCINT OUT + V1 t L RINT R2 FB R1 Vr D ROUT COUT The integrator amplifier generates a current, proportional to the DC errors between the FB voltage and Vr, which decreases the output voltage in order to compensate the total static error, including the voltage drop on PCB traces. In addition, CINT provides an AC path for the output ripple. In steady state, the voltage on COMP1/COMP2 pin is the sum of the reference voltage Vr and the output ripple (see Figure 30). In fact when the voltage on the COMP pin reaches Vr, a fixed Ton begins and the output increases. For example, we consider Vout = 5V with an output ripple of V = 50mV. Considering CINT >> CFILT, the CINT DC voltage drop VCINT is about 5V-Vr+25mV = 4.125V. CINT assures an AC path for the output voltage ripple. Then the COMP pin ripple is a replica of the output ripple, with a DC value of Vr + 25mV = 925mV. For more details about the output ripple compensation network, see the Section 7.13.6: Closing the integrator loop on page 37 in the Design guidelines. In steady state the FB pin voltage is about Vr and the regulated output voltage depends on the external divider: Equation 4 R2 OUT = Vr x 1 + ------ R 1 24/49 PM6680 Device description 7.4 Pulse skip mode If the SKIP pin is tied to ground, the device works in skip mode. At light loads a zero-crossing comparator truncates the low-side switch on-time when the inductor current becomes negative. In this condition the section works in discontinuous conduction mode. The threshold between continuous and discontinuous conduction mode is: Equation 5 ILOAD(SKIP) = VIN - VOUT x TON 2xL For higher loads the inductor current doesn't cross the zero and the device works in the same way as in PWM mode and the frequency is fixed to the nominal value. Figure 31. PWM and pulse skip mode inductor current PWM mode Inductor current Load current 0 Ton1 Toff Ton1=Ton2 Ton2 Pulse skip mode Low side on Toff Low side off Time Figure 31 shows inductor current waveforms in PWM and SKIP mode. In order to keep average inductor current equal to load current, in SKIP mode some switching cycles are skipped. When the output ripple reaches the regulated voltage Vreg, a new cycle begins. The off cycle duration and the switching frequency depend on the load condition. As a result of the control technique, losses are reduced at light loads, improving the system efficiency. 7.5 No-audible skip mode If SKIP pin is tied to VREF, a no-audible skip mode with a minimum switching frequency of 33 KHz is enabled. At light load condition, If there is not a new switching cycle within a 30us (typ.) period, a no-audible skip mode cycle begins. 25/49 Device description Figure 32. No audible skip mode PM6680 Inductor current No audible skip mode 30us Time 0 Low side The low side switch is turned on until the output voltage crosses about Vreg+1%. Then the high side MOSFET is turned on for a fixed on time period. Afterwards the low side switch is enabled until the inductor current reaches the zero-crossing threshold. This keeps the switching frequency higher than 33KHz. As a consequence of the control, the regulated voltage can be slightly higher than Vreg (up to 1%). If, due to the load, the frequency is higher than 33KHz, the device works like in skip mode. No-audible skip mode reduces audio frequency noise that may occur in pulse skip mode at very light loads, keeping the efficiency higher than in PWM mode. 7.6 Current limit The current-limit circuit employs a "valley" current-sensing algorithm. During the conduction time of the low side MOSFET the current flowing through it is sensed. The current-sensing element is the low side MOSFET on-resistance (Figure 33). Figure 33. RDSON sensing technique HS HGATE PHASE Rcsense CSENSE LS RDSon LGATE 26/49 PM6680 Device description An internal 100A current source is connected to CSENSE pin and determines a voltage drop on RCSENSE. If the voltage across the sensing element is greater than this voltage drop, the controller doesn't initiate a new cycle. A new cycle starts only when the sensed current goes below the current limit. Since the current limit circuit is a valley current limit, the actual peak current limit is greater than the current limit threshold by an amount equal to the inductor ripple current. Moreover the maximum output current is equal to the valley current limit plus half of the inductor ripple current: Equation 6 ILOAD (max) = ILvalley + IL 2 The output current limit depends on the current ripple, as shown in Figure 34: Figure 34. Current waveforms in current limit conditions Current Maximum load current is influenced by the inductor current ripple DC current limit = maximum load Inductor current Valley current threshold Time Being fixed the valley threshold, the greater the current ripple is, greater the DC output current is The valley current limit can be set with resistor RCSENSE: Equation 7 R CSENSE = R DSon x ILvalley ICSENSE Where ICSENSE = 100uA, RDSon is the drain-source on resistance of the low side switch. Consider the temperature effect and the worst case value in RDSon calculation. The accuracy of the valley current threshold detection depends on the offset of the internal comparator (VOFF) and on the accuracy of the current generator(VCSENSE): Equation 8 ILvalley ILvalley = R CSENSE R SNS I CSENSE VOFF + x 100 + + ICSENSE R SNS R CSENSE x ICSENSE R CSENSE 27/49 Device description PM6680 Where RSNS is the sensing element (RDSon) PM6680 provides also a fixed negative peak current limit to prevent an excessive reverse inductor current when the switching section sinks current from the load in PWM mode. This negative current limit threshold is measured between PHASE and SGND pins, comparing the magnitude drop on the PHASE node during the conduction time of the low side MOSFET with an internal fixed voltage of 120mV. If the current is sensed on the low side MOSFET, the negative valley-current limit INEG (if the device works in PWM mode) is given by: Equation 9 INEG = 120mV RDSon 7.7 Soft start and soft end Each switching section is enabled separately by asserting high EN1/EN2 pins respectively. In order to realize the soft start, at the startup the overcurrent threshold is set 25% of the nominal value and the undervoltage protection (see related sections) is disabled. The controller starts charging the output capacitor working in current limit. The overcurrent threshold is increased from 25% to 100% of the nominal value with steps of 25% every 700?s (typ.). After 2.8ms (typ.) the undervoltage protection is enabled. The soft start time is not programmable. A minimum capacitor CINT is required to ensure a soft start without any overshoot on the output: Equation 10 CINT 6uA ILvalley 4 I +L 2 x C out Figure 35. Soft start waveforms Switching output Current limit threshold EN1/EN2 Time 28/49 PM6680 Device description When a switching section is turned off (EN1/EN2 pins low), the controller enters in soft end mode.The output capacitor is discharged through an internal 18 P-MOSFET switch; when the output voltage reaches 0.3V, the low-side MOSFET turns on, keeping the output to ground. The soft end time also depends on load condition. 7.8 Gate drivers The integrated high-current drivers allow to use different power MOSFETs. The high side driver MOSFET uses a bootstrap circuit which is indirectly supplied by LDO5 output. The BOOT and PHASE pins work respectively as supply and return rails for the HS driver. The low side driver uses the internal LDO5 output for the supply rail and PGND pin as return rail. An important feature of the gate drivers is the adaptive anti-cross conduction protection, which prevents high side and low side MOSFETs from being on at the same time. When the high side MOSFET is turned off the voltage at the phase node begins to fall. The low side MOSFET is turned on when the voltage at the phase node reaches an internal threshold. When the low side MOSFET is turned off, the high side remains off until the LGATE pin voltage goes approximately under 1V. The power dissipation of the drivers is a function of the total gate charge of the external power MOSFETs and the switching frequency, as shown in the following equation: Equation 11 Pdriver = Vdriver x Q g x fsw Where Vdriver is the 5V driver supply. 7.9 Reference voltage and bandgap The 1.237V (typ.) internal bandgap voltage is accurate to 1% over the temperature range. It is externally available (VREF pin) and can supply up to 100A and can be used as a voltage threshold for the multifunction pins FSEL and SKIP to select the appropriate working mode. Bypass VREF to ground with a 100nF minimum capacitor. If VREF goes below 0.87V (typ.) , the system detects a fault condition and all the circuitry is turned off. A toggle on the input voltage (power on reset) or a toggle on SHDN pin is necessary to restart the device. An internal divider of the the bandgap provides a voltage reference Vr of 0.9V. This voltage is used as reference for the linear and the switching regulators outputs. The overvoltage protection, the undervoltage protection and the power good signals are referred to Vr. 29/49 Device description PM6680 7.10 Internal linear regulator The PM6680 has an internal linear regulator providing 5V (LDO5) at 2% accuracy. High side drivers, low side drivers and most of internal circuitry are supplied by LDO5 output through VCC pin (an external RC filter may be applied between LDO5 and VCC). The linear regulator can provide an average output current of 50mA and a peak output current of 100mA. Bypass LDO5 output with a minimum 1F ceramic capacitor and a 4,7F tantalum capacitor ( ESR 2). If the 5V output goes below 4V, the system detects a fault condition and all the circuitry is turned off. A power on reset or a toggle on SHDN pin is necessary to restart the device. V5SW pin allows to keep the 5V linear regulator always active or to enable the internal bootstrap-switch over function: if the 5V switching output is connected to V5SW, when the voltage on V5SW pin is above 4.8V, an internal 3.0 max p-channel MOSFET switch connects V5SW pin to LDO5 pin and simultaneously LDO5 shuts down. This configuration allows to achieve higher efficiency. V5SW can be connected also to an external 5V supply. LDO5 regulator turns off and LDO5 is supplied externally. If V5SW is connected to ground, the internal 5V regulator is always on and supplies LDO5 output. Table 7. V5SW GND V5SW multifunction pin Description The 5V linear regulator is always turned on and supplies LDO5 output. Switching 5V The 5V linear regulator is turned off when the voltage on V5SW is above 4.8V and output LDO5 output is supplied by the switching 5V output. External 5V supply The 5V linear regulator is turned off when the voltage on V5SW is above 4.8V and LDO5 output is supplied by the external 5V. 7.11 Power up sequencing and operative modes Let's consider SHDN, EN1 and EN2 low at the beginning. The battery voltage is applied as input voltage. The device is in shutdown mode. When the SHDN pin voltage is above the shutdown device on threshold (1.5V typ.), the controller begins the power-up sequence. All the latched faults are cleared. LDO5 undervoltage control is blanked for 4 ms and the internal regulator LDO5 turns on. If the LDO5 output is above the UVLO threshold after this time, the device enters in standby mode. The switching outputs are kept to ground by turning on the low side MOSFETs. When EN1 and EN2 pins are forced high the switching sections begin their soft start sequence. Table 8. Mode Run Operatives modes Conditions SHDN is high, EN1/EN2 pins are high Description Switching regulators are enabled; internal linear regulators outputs are enabled. Standby Shutdown Internal Linear regulators active (LDO5 is always on). Both EN1/EN2 pins are low In Standby mode LGATE1/LGATE2 pins are forced and SHDN pin is high high while HGATE1/HGATE2 pins are forced low. SHDN is low All circuits off. 30/49 PM6680 Device description 7.12 7.12.1 Monitoring and protections Power good signals The PM6680 provides three independent power good signals: one for each switching section (PGOOD1/PGOOD2). PGOOD1/PGOOD2 signals are low if the output voltage is out of 10% of the designed set point or during the soft-start, the soft end and when the device works in standby and shutdown mode. 7.12.2 Thermal protection The PM6680 has a thermal protection to preserve the device from overheating. The thermal shutdown occurs when the die temperature goes above +150C. In this case all internal circuitry is turned off and the power sections are turned off after the discharge mode. A power on reset or a toggle on the SHDN pin is necessary to restart the device. 7.12.3 Overvoltage protection When the switching output voltage is about 115% of its nominal value, a latched overvoltage protection occurs. In this case, the synchronous rectifier immediately turns on while the high-side MOSFET turns off. The output capacitor is rapidly discharged and the load is preserved from being damaged. The overvoltage protection is also active during the soft start. Once an overvoltage protection has been detected, a toggle on SHDN, EN1/EN2 pins or a power on reset is necessary to exit from the latched state. 7.12.4 Undervoltage protection When the switching output voltage is below 70% of its nominal value, a latched undervoltage protection occurs. In this case the switching section is immediately disabled and both switches are open. The controller enters in soft end mode and the output is eventually kept to ground, turning low side MOSFET on. The undervoltage circuit protection is enabled only at the end of the soft-start. Once an overvoltage protection has been detected, a toggle on SHDN, EN1/EN2 pin or a power on reset is necessary to clear the undervoltage fault and starts with a new soft-start phase. Table 9. Mode Overvoltage protection Undervoltage protection Thermal shutdown Protections and operatives modes Conditions Description LGATE1/LGATE2 pin is forced high, LDO5 remains OUT1/OUT2 > 115% of the active. Exit by a power on reset or toggling SHDN or nominal value EN1/EN2 OUT1/OUT2 < 70% of the nominal value TJ > +150C LGATE1/LGATE2 is forced high after the soft end mode, LDO5 remains active. Exit by a power on reset or toggling SHDN or EN1/EN2 All circuitry off. Exit by a POR on VIN or toggling SHDN. 31/49 Device description PM6680 7.13 Design guidelines The design of a switching section starts from two parameters: Input voltage range: in notebook applications it varies from the minimum battery voltage, VINmin to the AC adapter voltage, VINmax. Maximum load current: it is the maximum required output current, ILOAD(max). 7.13.1 Switching frequency It's possible to set 3 different working frequency ranges for the two sections with FSEL pin (Table 7 on page 30). Switching frequency mainly influences two parameters: Inductor size: for a given saturation current and RMS current, greater frequency allows to use lower inductor values, which means smaller size. Efficiency: switching losses are proportional to frequency. High frequency generally involves low efficiency. 7.13.2 Inductor selection Once that switching frequency is defined, inductor selection depends on the desired inductor ripple current and load transient performance. Low inductance means great ripple current and could generate great output noise. On the other hand, low inductor values involve fast load transient response. A good compromise between the transient response time, the efficiency, the cost and the size is to choose the inductor value in order to maintain the inductor ripple current IL between 20% and 50% of the maximum output current ILOAD(max). The maximum IL occurs at the maximum input voltage. With this considerations, the inductor value can be calculated with the following relationship: Equation 12 L= VIN - VOUT VOUT x fsw x IL VIN where fSW is the switching frequency, VIN is the input voltage, VOUT is the output voltage and IL is the selected inductor ripple current. In order to prevent overtemperature working conditions, inductor must be able to provide an RMS current greater than the maximum RMS inductor current ILRMS: Equation 13 ILRMS = (ILOAD (max)) 2 + Where IL(max) is the maximum ripple current: (IL (max)) 2 12 32/49 PM6680 Equation 14 Device description IL (max) = VIN max - VOUT V x OUT fsw x L VIN max If hard saturation inductors are used, the inductor saturation current should be much greater than the maximum inductor peak current Ipeak: Equation 15 Ipeak = ILOAD (max) + IL (max) 2 Using soft saturation inductors it's possible to choose inductors with saturation current limit nearly to Ipeak. Below there is a list of some inductor manufacturers. Table 10. Inductor manufacturer Series SER1360 MLC RLF12560 Inductor value (uH) 1 to 8 0.7 to 4.5 1 to 10 RMS current (A) 6 to 9.5 13.6 to 17.3 7.5 to 14.4 Saturation current (A) 7 to 31 11.5 to 26 7.5 to 18.5 Manufacturer COILCRAFT COILCRAFT TDK 7.13.3 Output capacitor The selection of the output capacitor is based on the ESR value Rout and the voltage rating rather than on the capacitor value Cout. The output capacitor has to satisfy the output voltage ripple requirements. Lower inductor value can reduce the size of the choke but increases the inductor current ripple IL. Since the voltage ripple VRIPPLEout is given by: Equation 16 VRIPPLEout = R out x IL A low ESR capacitor is required to reduce the output voltage ripple. Switching sections can work correctly even with 20mV output ripple. However, to reduce jitter noise between the two switching sections it's preferable to work with an output voltage ripple greater than 30mV. If lower output ripple is required, a further compensation network is needed (see Section 7.13.6: Closing the integrator loop on page 37). Finally the output capacitor choice deeply impacts on the load transient response (see Load transient response paragraph). Below there is a list of some capacitor manufacturers. 33/49 Device description PM6680 Table 11. Output capacitor manufacturer Series POSCAP TPB,TPD, TPE SPCAP UD, UE Capacitor value (uF) 100 to 470 100 to 470 Rated voltage (V) 2.5 to 6.3 2 to 6.3 ESR max (m) 12 to 65 7 to 18 Manufacturer SANYO PANASONIC 7.13.4 Input capacitors selection In a buck topology converter the current that flows into the input capacitor is a pulsed current with zero average value. The input RMS current of the two switching sections can be roughly estimated as follows: Equation 17 2 ICinRMS = D1 x I1 x (1 - D1 ) + D 2 x I2 x (1 - D 2 ) 2 Where D1, D2 are the duty cycles and I1, I2 are the maximum load currents of the two sections. Input capacitor should be chosen with an RMS rated current higher than the maximum RMS current given by both sections. Tantalum capacitors are good in term of low ESR and small size, but they occasionally can burn out if subjected to very high current during the charge. Ceramic capacitors have usually a higher RMS current rating with smaller size and they remain the best choice. Below there is a list of some ceramic capacitor manufacturers. Table 12. Input capacitor manufacturer Series UMK325BJ106KM-T GMK325BJ106MN C3225X5R1E106M Capacitor value (uF) 10 10 10 Rated voltage (V) 50 35 25 Manufacturer TAYIO YUDEN TAYIO YUDEN TDK 34/49 PM6680 Device description 7.13.5 Power MOSFETs Logic-level MOSFETs are recommended, since low side and high side gate drivers are powered by LDO5. Their breakdown voltage VBRDSS must be higher than VINmax. In notebook applications, power management efficiency is a high level requirement. The power dissipation on the power switches becomes an important factor in switching selections. Losses of high-side and low-side MOSFETs depend on their working conditions. The power dissipation of the high-side MOSFET is given by: Equation 18 PDHighSide = Pconduction + Pswitching Maximum conduction losses are approximately: Equation 19 Pconduction = R DSon x VOUT x ILOAD (max) 2 VIN min where RDSon is the drain-source on resistance of the high side MOSFET. Switching losses are approximately: Equation 20 Pswitching = VIN x (ILOAD (max) - IL I ) x t on x fsw VIN x (ILOAD (max) + L ) x t off x fsw 2 2 + 2 2 where ton and toff are the switching times of the turn off and turn off phases of the MOSFET. As general rule, high side MOSFETs with low gate charge are recommended, in order to minimize driver losses. Below there is a list of possible choices for the high side MOSFET. Table 13. High side MOSFET manufacturer Type STS12NH3LL STS17NH3LL Gate charge (nC) 10 18 Rated reverse voltage (V) 30 30 Manufacturer ST ST The power dissipation of the low side MOSFET is given by: Equation 21 PDLowSide = Pconduction Maximum conduction losses occur at the maximum input voltage: 35/49 Device description Equation 22 PM6680 V Pconduction = RDSon x 1 - OUT VIN max x ILOAD (max)2 Choose a synchronous rectifier with low RDSon. When high side MOSFET turns on, the fast variation of the phase node voltage can bring up even the low side gate through its gatedrain capacitance CRSS, causing cross-conduction problems. Choose a low side MOSFET that minimizes the ratio CRSS/CGS (CGS = CISS - CRSS). Below there is a list of some possible low side MOSFETs. Table 14. Low side MOSFET manufacturer Type STS17NF3LL STS25NH3LL RDSon (m) 5.5 3.5 CRSS C GS Manufacturer ST ST Rated reverse voltage (V) 30 30 0.047 0.011 Dual n-channel MOSFETS can be used in applications with a maximum output current of about 3 A. Below there is a list of some MOSFET manufacturers. Table 15. Dual MOSFET manufacturer Type STS8DNH3LL STS4DNF60L RDSon (m) 25 65 Gate charge (nC) 10 32 Rated reverse voltage (V) 30 60 Manufacturer ST ST A rectifier across the low side MOSFET is recommended. The rectifier works as a voltage clamp across the synchronous rectifier and reduces the negative inductor swing during the dead time between turning the high-side MOSFET off and the synchronous rectifier on. It can increase the efficiency of the switching section, since it reduces the low side switch losses. A shottky diode is suitable for its low forward voltage drop (0.3V). The diode reverse voltage must be greater than the maximum input voltage VINmax. A minimum recovery reverse charge is preferable. Below there is a list of some shottky diode manufacturers. Table 16. Shottky diode manufacturer Series STPS1L30M STPS1L20M Forward voltage (V) 0.34 0.37 Rated reverse voltage (V) 30 20 Reverse current (uA) 0.00039 0.000075 Manufacturer ST ST 36/49 PM6680 Device description 7.13.6 Closing the integrator loop The design of external feedback network depends on the output voltage ripple. If the ripple is higher than approximately 30mV, the feedback network (Figure 35) is usually enough to keep the loop stable. Figure 36. Circuitry for output ripple compensation COMP PIN VOLTAGE Vr t OUTPUT VOLTAGE ? V ? V Vr COMP I=gm(V1-Vr) + PW M Comparator gm + VCINT RINT t L OUT Vr V1 CFILT CINT ROUT D COUT R2 FB R1 The stability of the system depends firstly on the output capacitor zero frequency. The following condition should be satisfied: Equation 23 fsw > k x fZout = k 2 x C out x R out where k is a design parameter greater than 3 and Rout is the ESR of the output capacitor. It determinates the minimum integrator capacitor value CINT: Equation 24 CINT > gm Vr x fsw VOUT 2 x - fZout k where gm = 50us is the integrator transconductance. In order to ensure stability it must be also verified that: Equation 25 C INT > gm Vr x 2 x fZout VOUT 37/49 Device description PM6680 In order to reduce ground noise due to load transient on the other section, it is recommended to add a resistor RINT and a capacitor Cfilt that, together with CINT, realize a low pass filter (see Figure 36). The cutoff frequency fCUT must be much greater (10 or more times) than the switching frequency of the section: Equation 26 R INT = 2 x fCUT 1 C x C filt x INT C INT + C filt Due to the capacitive divider (CINT, Cfilt), the ripple voltage at the COMP pin is given by: Equation 27 VRIPPLEINT = VRIPPLEout x CINT = VRIPPLEout x q CINT + Cfilt Where VRIPPLEout is the output ripple and q is the attenuation factor of the output ripple. If the ripple is very small (lower than approximately 30mV), a further compensation network, named virtual ESR network, is needed. This additional part generates a triangular ripple that is added to the ESR output voltage ripple at the input of the integrator network. The complete control schematic is represented in Figure 37. Figure 37. Virtual ESR network COMP PIN VOLTAGE Vr t t ? V1 T NODE VOLTAGE ? V1 OUTPUT VOLTAGE ?V CFILT COMP Vr + - PWM t R1 T RINT CINT gm Vr Comparator + V1 - C L R ROUT R2 R1 OUT FB D COUT 38/49 PM6680 Device description The T node voltage is the sum of the output voltage and the triangular waveform generated by the virtual ESR network. In fact the virtual ESR network behaves like a further equivalent ESR RESR. A good trade-off is to design the network in order to achieve an RESR given by: Equation 28 RESR = VRIPPLE - Rout IL where IL is the inductor current ripple and VRIPPLE is the overall ripple of the T node voltage. It should be chosen higher than approximately 30mV. The new closed loop gain depends on CINT. In order to ensure stability it must be verified that: Equation 29 C INT > Where: Equation 30 gm Vr x 2 x fZ VOUT fZ = 1 2 x C out x R TOT where RTOT is the sum of the ESR of the output capacitor Rout and the equivalent ESR given by the virtual ESR network RESR. Moreover CINT must meet the following condition: Equation 31 fsw > k x fZ = k 2 x C out x R TOT Where k is a free design parameter greater than 3 and determines the minimum integrator capacitor value CINT: Equation 32 CINT > gm Vr x VOUT fsw 2 x k - fZ C must be selected as shown: Equation 33 C > 5 x C INT 39/49 Device description PM6680 R must be chosen in order to have enough ripple voltage on integrator input: Equation 34 R= R1 can be selected as follows: Equation 35 L RESR x C 1 Rx Cx x f Z R1 = 1 R- C x x fZ Example: OUT1 = 1.5V, fSW = 290KHz, L = 2.5uH, Cout = 330uF with Rout 12m. We design RESR = 12mW. We choose CINT = 1nF by equations 30, 33 and Cfilt = 47pF, RINT = 1K by eq.27, 28. C = 5.6nF by Eq.34. Then R = 36K (eq.35) and R1 = 3K (eq.36). 7.13.7 Other parts design VIN filter A VIN pin low pass filter is suggested to reduce switching noise. The low pass filter is shown in the next figure: Figure 38. VIN pin filter R Input voltage VIN C 100pF Typical components values are: R = 3.9 and C = 4.7uF. VCC filter A VCC low pass filter helps to reject switching commutations noise: 40/49 PM6680 Figure 39. Inductor current waveforms LDO5 R C VC C Device description Typical components values are: R=47 and C = 1uF. VREF capacitor A 10nF to 100nF ceramic capacitor on VREF pin must be added to ensure noise rejection. LDO5 output capacitors Bypass the output of each linear regulator with 1uF ceramic capacitor closer to the LDO pin and a 4.7uF tantalum capacitor (ESR = 2). In most applicative conditions a 4.7uF ceramic output capacitor can be enough to ensure stability. Bootstrap circuit The external bootstrap circuit is represented in the next figure: Figure 40. Bootstrap circuit D RBOOT CBOOT LDO5 BOOT PHASE L The bootstrap circuit capacitor value CBOOT must provide the total gate charge to the high side MOSFET during turn on phase. A typical value is 100nF. The bootstrap diode D must charge the capacitor during the off time phases. The maximum rated voltage must be higher than VINmax. A resistor RBOOT on the BOOT pin could be added in order to reduce noise when the phase node rises up, working like a gate resistor for the turn on phase of the high side MOSFET. 41/49 Device description PM6680 7.13.8 Design example The following design example considers an input voltage from 7V to 16V. The two switching outputs are OUT1=1.5V and OUT2=1.05V and must deliver a maximum current of 5A. The selected switching frequencies are about 290kHz for OUT1 section and about 425kHz for OUT2 section (see Table 7 on page 30). 1. Inductor selection OUT1: ILOAD = 5A, 35% ripple current. Equation 36 L= 1.5V (16V - 1.5V) 2.5H 290KHz 16V 0.35 5 We choose standard value L = 2.5 uH. IL(max) = 1.8A @VIN =12V ILRMS = 5.03A IPEAK = 5A + 0.9A = 5.9A OUT2: ILOAD = 5A, 30% ripple current. Equation 37 L= 1.05V (16V - 1.05V) 1.6H 425KHz 16V 0.3 5 IL(max) = 1.6A @VIN = 12V. ILRMS = 5.02A IPEAK = 5A + 0.8A = 5.8A 2. Output capacitor selection We would like to have an output ripple smaller than 25mV. OUT1: POSCAP 6TPB330M OUT2: POSCAP 6TPB330M 3. Power MOSFETS OUT1: High side: STS12NH3LL Low side: STS12NH3LL OUT2:High side: STS12NH3LL Low side: STS12NH3LL 4. Current limit OUT1: Equation 38 ILvalley (min) = ILOAD (max) - IL (min) = 4.12A 2 42/49 PM6680 Equation 39 Device description RCSENSE 4.12A 16.25m 670 100A (Let's assume the maximum temperature Tmax = 75C in RDSon calculation) OUT2: Equation 40 ILvalley (min) = ILOAD (max) - IL (min) = 4.2A 2 Equation 41 RCSENSE 4 .2 A 16.25m 680 100A (Let's assume Tmax = 75C in RDSon calculation) 5. Input capacitor Maximum input capacitor RMS current is about 2.8A. Then ICinRMS > 2.8A. We put three 10uF ceramic capacitors with Irms = 1.5A. 6. Synchronous rectifier OUT1: Shottky diode STPS1L30M OUT2: Shottky diode STPS1L30M 7. Integrator loop (Refer to Figure 37) OUT1: The ripple is smaller than 40mV, then the virtual ESR network is required. CINT = 1nF; Cfilt = 47pF; RINT =1k C = 5.6nF; R= 36k; R1 = 3k OUT2: The ripple is smaller than 40mV, then the virtual ESR network is required. CINT = 1nF; Cfilt = 110pF; RINT = 1k C = 5.6nF; R = 22k; R1 = 3.3k 8. Output feedback divider (Refer to Figure 30 on page 24) OUT1: R1 = 10k; R2 = 6.8k OUT2: R1 = 11k; R2 = 1.8k 9. Layout guidelines The layout is very important in terms of efficiency, stability and noise of the system. It is possible to refer to the PM6680 demoboard for a complete layout example. For good PC board layout follows these guidelines: Place on the top side all the power components (inductors, input and output capacitors, MOSFETs and diodes). Refer them to a power ground plan, PGND. If possible, reserve a layer to PGND plan. The PGND plan is the same for both the switching sections. AC current paths layout is very critical (see Figure 41 on page 44). The first priority is to minimize their length. Trace the LS MOSFET connection to PGND plan as short as 43/49 Device description PM6680 possible. Place the synchronous diode D near the LS MOSFET. Connect the LS MOSFET drain to the switching node with a short trace. Place input capacitors near HS MOSFET drain. It is recommended to use the same input voltage plan for both the switching sections, in order to put together all input capacitors. Place all the sensitive analog signals (feedbacks, voltage reference, current sense paths) on the bottom side of the board or in an inner layer. Isolate them from the power top side with a signal ground layer, SGND. Connect the SGND and PGND plans only in one point (a multiple vias connection is preferable to a 0 ohm resistor connection) near the PGND device pin. Place the device on the top or on the bottom size and connect the exposed pad and the SGND pins to the SGND plan (see Figure 41). Figure 41. Current paths, ground connection and driver traces layout As general rule, make the high side and low side drivers traces wide and short. The high side driver is powered by the bootstrap circuit. It's very important to place capacitor CBOOT and diode DBOOT as near as possible to the HGATE pin (for example on the layer opposite to the device). Route HGATE and PHASE traces as near as possible in order to minimize the area between them. The Low side gate driver is powered by the 5V linear regulator output. Placing PGND and LGATE pins near the low side MOSFETs reduces the length of the traces and the crosstalk noise between the two sections. The linear regulator output LDO5 is referred to SGND as long as the reference voltage Vref. Place their output filtering capacitors as near as possible to the device. Place input filtering capacitors near VCC and VIN pins. It would be better if the feedback networks connected to COMP, FB and OUT pins are "referred" to SGND in the same point as reference voltage Vref. To avoid capacitive 44/49 PM6680 Device description coupling place these traces as far as possible from the gate drivers and phase (switching) paths. Place the current sense traces on the bottom side. If low side MOSFET RDSon sensing is enabled, use a dedicated connection between the switching node and the current limit resistor RCSENSE. 45/49 Package mechanical data PM6680 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 17. VFQFPN 5x5x1.0 32L Pitch 0.50 Databook (mm) Dim. Min A A1 A3 b D D2 E E2 e L ddd 0.3 4.85 0.18 4.85 0.8 0 Typ 0.9 0.02 0.2 0.25 5 See exposed pad variations 5 See exposed pad variations 0.5 0.4 0.5 0.05 (2) (2) Max 1 0.05 0.3 5.15 5.15 Table 18. Exposed pad variations (1)(2)D2 E2 Max 3.20 Min 2.90 Typ 3.10 Max 3.20 Min 2.90 Typ 3.10 1. VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead. Very thin: A = 1.00mm Max. 2. Dimensions D2 & E2 are not in accordance with JEDEC. 46/49 PM6680 Figure 42. Package dimensions Package mechanical data 47/49 Revision history PM6680 9 Revision history Table 19. Date 17-Mar-2006 10-May-2006 29-Jun-2006 28-Jul-2006 25-Oct-2006 28-Aug-2007 Document revision history Revision 1 2 3 4 5 6 Initial release Few updates Mechanical data updated Application schematic updated Figure 27 on page 16 Changes electrical characteristics, added COMP value skip mode, Order code table updated Updated: Current sensing option and Absolute Maximum Ratings Changes 48/49 PM6680 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 49/49 |
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